Programmable logic devices (PLDs) are a class of integrated circuits (ICs) which can be programmed by a user to implement the user's logic functions. PLDs are often used in electronic systems because, unlike custom hardwired or "application specific" integrated circuits (ASICs), PLDs can be programmed in a relatively short amount of time, and often can be reprogrammed quickly to incorporate modifications to the implemented logic function.
One major class of PLDs are referred to as programmable logic array (PLA) devices or programmable array logic (PAL) devices. Basically, these early PLDs include an AND plane which ANDs two or more input signals to produce product terms (P-terms), and an OR plane which ORs two or more of the P-terms generated by the AND plane. The AND plane is typically formed as a matrix of programmable connections where each column connects to an input pin of the PLD, and each row forms a P-term which is transmitted to the OR plane. The OR plane may be programmable (i.e., each P-term is programmably connectable to one of several different OR plane outputs), in which case the PLD is referred to as a PLA device. Alternatively, the OR plane may be fixed (i.e., each P-term is assigned to a particular OR plane output), in which case the PLD is referred to as a PAL device. The AND plane and OR plane of PLA and PAL devices implement logic functions represented in the sum-of-products form.
PLA and PAL devices were well-received by logic designers when their implemented logic functions were relatively small. However, as logic functions grew increasingly larger and more complex, logic designers were required to wire together two or more small PLDs to provide sufficient logic capacity. Although this process was tolerated during development and testing, it increased the cost and size of production units. This generated a demand for PLDs with increasingly larger logic capacity.
To meet the ever-increasing demand for greater capacity, PLDs with increasingly complex architectures have been developed. One popular complex PLD type, known as complex programmable logic devices (CPLDs), includes two or more function blocks connected together and to input/output (I/O) modules by an interconnect matrix such that each of the function blocks selectively communicates with the I/O modules and with other function blocks of the CPLD through the interconnect matrix. Each function block of the CPLD is structured like the two-level PLDs, described above. In effect, these CPLDs incorporate several early PLDs and associated connection circuitry onto a single integrated circuit. This provides a circuit designer the convenience of implementing a complex logic function using a single IC.
Each function block of an early CPLD typically includes an AND array and a set of macrocells. The AND array includes a set of input lines for receiving input signals from the interconnect matrix, and a set of product term (P-term) lines for transmitting P-term signals to the macrocells. Each P-term line is connected to the input lines using programmable connections which allow logic ANDing of two or more of the input signals. Each macrocell includes an OR gate which is programmable to receive one or more of the P-term signals transmitted on the P-term lines. The OR gate of each macrocell produces a sum-of-products term which is either transmitted to the I/O modules of the CPLD, fed back through the interconnect matrix, or is transmitted on special lines to an adjacent macrocell.
Some CPLDs, such as XC7300 series CPLDs and XC9500 series CPLDs produced by Xilinx, Inc. of San Jose, Calif., incorporate "cross-point" interconnect matrices. Cross-point interconnect matrices include a plurality of parallel word (input) lines arranged perpendicular to a plurality of parallel bit (output) lines. At the intersections of the word lines and bit lines are programmable connection circuits. Each programmable connection includes a memory cell which is programmed to either connect or disconnect one word line to/from one bit line. The word lines receive signals input to the CPLD, and feedback signals from the macrocells. Selected bit lines are connected to the word lines via the programmable connections to route input and feedback signals into selected function blocks. Cross-point interconnect matrices are characterized in that every word line is programmably connectable to every bit line, thereby providing the advantage of 100% routability--that is, every word line can be connected to every bit line within a cross-point interconnect matrix. Another advantage of cross-point interconnect matrices is that two or more signals on the word lines can be logically ANDed together before transmission to the function blocks. One cross-point interconnect matrix is described in U.S. Pat. No. 5,028,821, and is also described in co-owned U.S. Pat. No. 5,530,378, which is incorporated herein in its entirety.
Long time users of CPLDs are aware of switching (coupling) noises in the interconnect matrix when multiple unrelated word lines are switched concurrently. This noise is believed to occur because of two primary phenomena: a) capacitive coupling between word lines and bit lines of the interconnect matrix, and b) noise on the internal power buses of the CPLD because of excessive concurrent word line switching. The result of this switching noise is a reduced effective clock rate of approximately 30% in typical cases.
Capacitive coupling occurs, for example, when word line voltage potentials are simultaneously shifted from high to low, or from low to high. As an example, when several macrocells of an CPLD implement a counter, the output signals from all of these macrocells switch from high to low when the counter "turns over" (i.e., every macrocell simultaneously shifts from a "1" to a "0"). In addition, the counter is typically driven by a common clock signal, so that all of the macrocells switch concurrently. Concurrent multiple switching events also occur when several macrocells are cleared simultaneously. These concurrent multiple macrocell switching events cause a large capacitive effect (coupling) between the bit lines and word lines of the CPLD, thereby resulting in bit line noise.
Noise also occurs on the internal power buses when a large number of word lines are switched simultaneously from high to low, or from low to high. Simultaneous switching creates a crowbar effect which causes large fluctuations in the voltage level of the power buses.
One known method of addressing the issue of noise produced by concurrent multiple macrocell switching events is disclosed in U.S. Pat. No. 5,617,041. The disclosed method recognizes that, when an CPLD is used to implement a logic function, several of the CPLD's macrocells are typically not utilized to implement the logic function. In accordance with the method disclosed in U.S. Pat. No. 5,617,041, these unused macrocells are programmed to transmit feedback signals into the interconnect matrix which are opposite in polarity with commonly clocked word line switching signals, thereby producing counteractive word line switching signals which reduces switching noise in the interconnect matrix.
A problem with the method disclosed in U.S. Pat. No. 5,617,041 is that it relies on the availability of unused macrocells. In applications where there are only a few unused macrocells, the method typically cannot produce sufficient counteractive signals to significantly reduce switching noise. In addition, even if there are unused macrocells available, the software will be required to map the logic required for the specified equation into the macrocell. This is not always possible because of the input and P-term restrictions due to the CPLD architecture. Further, in applications where low power consumption is important, the utilization of otherwise unused macrocells to produce counteractive word line switching signals significantly increases power consumption of the CPLD.